1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of controllably etching a semiconductor wafer.
2. Description of the Related Art
In general, semiconductor devices are manufactured by forming many process layers comprised of various materials above a semiconducting substrate, and, thereafter, removing selected portions of the layers, i.e., patterning the layers. This patterning may be accomplished using known photolithography and etching processes to define the various features of the device, e.g., the gate insulation layer, the gate electrode, metal lines and contacts, etc. This forming and patterning of the process layers is typically performed layer by layer as the individual layers are formed, although multiple layers may be patterned at any given time.
Photolithography is a common process used in patterning these various layers. Photolithography typically involves the use of a product known as photoresist. In general terms, photoresist is a product whose solubility in a developer may be manipulated by exposure to a light source. There are positive and negative photoresists currently available on the market.
In general, the photolithography process involves forming a layer of photoresist above a previously formed process layer, and exposing selected portions of the layer of photoresist to a light source to form a pattern in the photoresist that is desired to be formed in the under-lying process layer. All of these steps are typically performed in well-known photolithography modules that include a section for depositing the photoresist on the wafer, e.g., a spin-coating station, a device for selectively exposing portions of the photoresist layer to a light source through a reticle, e.g., a stepper, and a section for rinsing and developing the photoresist layer after it has been selectively exposed to the light source. Thereafter, an etching process, such as a plasma etching process, is performed to remove portions of the underlying process layer that are not covered by the patterned layer of photoresist, i.e., the patterned layer of photoresist acts as a mask. After the etching process is complete, the patterned photoresist layer is removed so that additional process layers may be formed above the now go patterned process layer.
One significant aspect in semiconductor device manufacturing involves controlling material removal processes, such as etching. Generally, most features on a semiconductor device are formed by depositing layers of material (e.g., conductive or insulative) and patterning the layers using photolithography and etch processes. There are many variables that affect the accuracy and repeatability of the material removal processes used to form the features. One particular type of material removal tool uses a plasma etch process to perform a primarily anisotropic etch to form features on a semiconductor wafer. Certain etch recipes involve controlling the duration of the etch using a predetermined time. For such a timed etch to be robust, the etch rate of the tool must be predictable and repeatable. Other etch recipes proceed with the etch until an endpoint determination is made. Various techniques are available for detecting etch endpoints. For example, during a plasma etch process the plasma chemistry noticeably changes when a top layer is etched through and the tool begins to etch the underlying layer. The chemistry of the etch chamber is monitored, using for instance an optical emission spectrometer, and the etch is terminated when the change in chemistry is detected. Some etching processes involve the use of both a timed etch process to remove the bulk of the material and an endpoint determination process to determine when processing is complete.
As technology improvements facilitate smaller critical dimensions for semiconductor devices, the need to reduce errors increases dramatically. Proper formation of sub-sections within a semiconductor device is an important factor in ensuring proper performance of the manufactured semiconductor device. Critical dimensions of the sub-sections generally have to be within a predetermined acceptable margin of error for semiconductor devices to be within acceptable manufacturing quality.
Conventional etching processes suffer from a number of deficiencies. For example, conventional etching does not account for spatial variations in the rates of removal of the process layer. That is, the etching process may remove material faster in certain regions of the wafer, and slower in other regions. For example, the etching process may completely remove the process layer at the edge of the wafer, while the process layer remains at the center of the wafer, or vice versa. With the advent of larger wafers (e.g., some manufacturers are in the process of moving to twelve inch wafers), the problem of spatial variations is exacerbated. Moreover, since the endpoint may not be signaled until all, or substantially all, of the process layer is removed, portions of underlying process layers in areas where the process layer has been removed first may be unnecessarily subjected to more of the etching process than would otherwise be necessary.
The present invention is directed to a method that minimizes or reduces some or all of the aforementioned problems.
The present invention is directed to a system. The system is comprised of a semiconductor processing tool, an etcher, a metrology tool, and a controller. The semiconductor processing tool is capable of forming a process layer above a semiconducting substrate. The etcher is capable of removing at least a portion of the process layer. The metrology tool is capable of measuring a first depth of the etch at a first location in a first preselected region of the semiconducting substrate. The controller is capable of comparing the first depth to a desired depth, and varying the temperature of a subsequently processed semiconducting substrate in a region corresponding to the first preselected region in response to the first depth being different from the desired depth.
In another aspect of the instant invention, a method is provided. The method is comprised of forming a process layer above a semiconducting substrate; etching at least a portion of said process layer; and measuring a first depth of the etch at a first location in a first preselected region of the semiconducting substrate. Thereafter, the first depth is compared to a desired depth, and the temperature of a subsequently processed semiconducting substrate in a region corresponding to the first preselected region is varied in response to the first depth being different from the desired depth.